Performance Verification of a Real-Time Digital Signal 
Processing System Based on FPGA

Sen Du; Qian Mao

doi:10.70711/aitr.v3i3.8034

Performance Verification of a Real-Time Digital Signal Processing System Based on FPGA

Sen Du, Qian Mao

Abstract

To evaluate the performance of FPGA in real-time digital signal processing, an experimental system was constructed and tested.
The design adopts a co-design approach of RTL and HLS, combined with hierarchical clocking and a double-buffering mechanism, to accelerate hardware implementation of algorithms such as FFT and filtering. Experimental results show that at a single-channel rate of 1 GSps,
the system achieves a throughput of 2.03 Gbps with a latency of 3.42 ?s. In eight-channel mode, throughput reaches 8.12 Gbps with a power
consumption of 21.5 W. Functional verification confirmed consistency between output and simulation, while demodulation accuracy met communication requirements, demonstrating the efficiency and reliability of FPGA-based real-time processing.

Keywords

Fpga; Real-Time Digital Signal Processing; Performance Verification; Experimental Platform

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DOI: http://dx.doi.org/10.70711/aitr.v3i3.8034

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